Search results for "Very-large-scale integration"
showing 10 items of 21 documents
Numerical approximation of mixed models for digital integrated circuits
1991
To analyse an electrical network many CAD (Computer Aided Design) circuit simulators are available today. The most well-known is probably SPICE -Nagel [1975]. Although this type of simulator is able to precisely compute the transient performances (as delay time), the usage of complete models of devices implies an extremely high time consumption. So, the circuit simulators are unappropriate for the initial stage of VLSI design where a high speed timing analyser (“timing simulator”) is required. To this goal, alternative approaches using either simpler device models or simpler numerical algorithms or easily computable formulae for delay time approximation, have been developed in the past deca…
New statistical post processing approach for precise fault and defect localization in TRI database acquired on complex VLSI
2013
International audience; Timing issue, missing or extra state transitions or unusual consumption can be detected and localized by Time Resolved Imaging (TRI) database analysis. Although, long test pattern can challenge this process. The number of photons to process rapidly increases and the acquisition time to have a good signal over noise ratio (SNR) can be prohibitive. As a result, the tracking of the defect emission signature inside a huge database can be quite complicated. In this paper, a method based on data mining techniques is suggested to help the TRI end user to have a good idea about where to start a deeper analysis of the integrated circuit, even with such complex databases.
Optical Probing (EOFM/TRI): A large set of complementary applications for ultimate VLSI
2013
International audience; Electro Optical Techniques (EOFM: Electro Optical Frequency Mapping and EOP: Electro Optical Probing) and Dynamic Light Emission Techniques (TRE: Time Resolved Emission and TRI: Time Resolved Imaging) are dynamic optical probing techniques widely used at IC level for design debug and defect localization purpose. They can pinpoint the origin of timing issue or logic fault in up to date CMOS devices. Each technique has its advantages and its drawbacks allowing a common set of applications and more specific ones. We have been involved in the development of the most advanced techniques related to EOFM and TRI on various devices (down to 28nm technology). What we can expe…
Handling precedence constraints in scheduling problems by the sequence pair representation
2015
In this paper, we show that sequence pair (SP) representation, primarily applied to the rectangle packing problems appearing in the VLSI industry, can be a solution representation of precedence constrained scheduling. We present three interpretations of sequence pair, which differ in complexity of schedule evaluation and size of a corresponding solution space. For each interpretation we construct an incremental precedence constrained SP neighborhood evaluation algorithm, computing feasibility of each solution in the insert neighborhood in an amortized constant time per examined solution, and prove the connectivity property of the considered neighborhoods. To compare proposed interpretations…
Operational experience with a large detector system using silicon strip detectors with double sided readout
1992
Abstract A large system of silicon strip detectors with double sided readout has been successfully commissioned over the course of the last year at the e + e − collider LEP. The readout of this 73 728 channel system is performed with custom designed VLSI charge sensitive amplifier chips (CAMEX64A). An overall point resolution of 12 μm on both sides has been acheived for the complete system. The most important difficulties during the run were beam losses into the detector, and a chemical agent deposited onto the electronics; however, the damage from these sources was understood and brought under control. This and other results of the 1991 data-taking run are described with special emphasis o…
Full Wave Solution for Intel CPU With a Heat Sink for EMC Investigations
2010
A CPU with a heat sink (e.g. Intel Pentium 4 and Intel Pentium dual core) is a challenging problem for EMC analysis. A Very Large Scale Integrated (VLSI) device was modelled using the Finite Element Method (FEM) frequency domain solver to obtain a 3D full wave solution. The electromagnetic (EM) radiation emitted from these high power microelectronic circuits connected to a heat sink was found to have resonant frequencies around 2.4 GHz and 5 GHz with reflection coefficients less than -19 dB and -8 dB respectively. These resonant frequencies are very close to the operating frequency of both IEEE and Bluetooth wireless communication systems. This paper proposes a new benchmark model based on …
Self-organizing maps: A new digital architecture
1991
An original hardware architecture implementing the self-organizing feature maps, which is one of the most powerful and efficent neural network algorithm, is presented. The architecture, contrary to the most investigated hardware implementations of neural networks, is a full digital one and it may be easily built by using the standard VLSI techniques.
Implementation of compact VLSI FitzHugh-Nagumo neurons
2008
In this paper we show a low power and very compact VLSI implementation of a FitzHugh-Nagumo neuron for large network implementations. The circuit consists of only 17 small transistors and two capacitors and consumes less than 23 muW. It is composed of a nonlinear resistor and a lossy active inductor. We demonstrate that a simple low Q active inductor can be used instead of a complex one because the parasitic series resistor can be easily embedded to the FitzHugh-Nagumo model. We also perform a statistical analysis to check the robustness of the circuit against mismatch.
The PAPIA system
1991
In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operatio…
Realistic model of compact VLSI FitzHugh–Nagumo oscillators
2013
In this article, we present a compact analogue VLSI implementation of the FitzHugh–Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off freque…